This application relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a physically shared data path, and a test device for the same.
State of the art semiconductor memory devices can include a stacked set of chips that are accessed by a controller or other external device via a shared data path. For example, a stacked chip semiconductor package may include a plurality of chips stacked vertically, where similar elements of different chips are physically and electrically connected via a shared data path using, for example, a through silicon via (TSV) or a common node on a substrate. Typically, in a semiconductor memory device having a physically shared data path among a set of chips, testing of data written to the chips via the shared data path is accomplished by sequentially accessing and testing each chip, and cannot be simultaneously performed by the chips. Such a method may, however, increase the amount of time needed to test these types of semiconductor devices, thereby slowing down the manufacturing process.